As the operational complexity of integrated circuit memory devices increases, the demands on the testing of the integrated circuit memory devices may also increase. Accordingly, techniques to reduce the requirements of integrated circuit memory device testers have been researched, including techniques for simultaneously testing multiple integrated circuit memory devices during the manufacturing process.
FIG. 1 is a block diagram of an operation control circuit according to the prior art. A system clock (CLK) may be provided to the integrated circuit memory device operating in a synchronous mode. A clock enable signal (CKE) may also be provided to the integrated circuit memory device to enable and disable the generation of an internal clock for operation during a synchronous mode. The system clock and the clock enable signal may be combined to produce the internal clock (PCLK) synchronous to the system clock. The internal clock may then be enabled upon the assertion of CKE and disabled during the deassertion of CKE. In particular, the clock enable may be provided to an internal clock enable signal generator 14 via a first input buffer 10. Similarly, the system clock may be provided to an internal clock generator 16 via a second input buffer 12.
FIG. 2 is a circuit diagram of an input buffer in an integrated circuit memory device according to the prior art. In particular, the input buffer may be used to implement the first input buffer 10 and second input buffer 12 in FIG. 1. The input buffer may be constructed using differential amplifiers so that the input buffer generates an output signal having a phase which is the opposite of a signal applied to the input buffer. For example, in FIG. 1, the second input buffer 12 inverts the system clock, to provide the PCLKTTL signal. Furthermore, the input buffer may convert the voltage level of the input signal. For example, the second input buffer 12 may convert a system clock having a TTL voltage level to a PLCKTTL having a CMOS voltage level.
FIG. 3 is a circuit diagram of an internal clock enable signal generator 14 of FIG. 1. The clock enable signal generator 14 receives the PCKETTL signal from the first input buffer 10, and generates a synchronous PCLK enable signal (PCKE). The PCKE signal is synchronous to the operation of a CLKA signal. The CLKA signal is an internal clock signal generated synchronous with PCLKTTL. The clock enable signal generator 14, therefore, may create a synchronous PCKE signal that is valid for a number of CLKA time periods. The synchronous PCKE may then be used to generate a synchronous PCLK signal for the synchronous operation of the integrated circuit memory device.
FIG. 4 is a circuit diagram of an internal clock generator 16 according to the prior art. The internal clock generator 16 generates the synchronous CLKA from the PCLKTTL signal. The internal clock generator 16 also generates a synchronous PCLK signal from the PCLKTTL and the synchronous PCKE signal.
FIG. 5 is a circuit diagram of an internal operation signal generation circuit according to the prior art. The internal operation signal generation circuit provides synchronized control signals for the synchronous operation of the integrated circuit memory device. In particular, the internal operation signal generation circuit may receive various control signals provided to the integrated circuit memory via the input buffers shown in FIG. 1. Accordingly, the internal operation signal generation circuit generates corresponding control signals synchronous with the operation of the PCLK signal.
FIG. 6 is a timing diagram of operations of an operation control circuit according to the prior art. In particular, FIG. 6 illustrates operations in a case wherein the clock enable signal CKE is disabled for a predetermined time and later enabled. When the CKE signal becomes low, the PCKETTL signal transitions to high after a predetermined time, and the PCKE signal becomes low on the falling edge of the CLKA signal. Thus, the PCKE signal is generated synchronously with the CLKA signal. When the PCKE signal becomes low, the generation of the PCLK signal is terminated. However, when the PCKE signal later transitions to a high, the generation of the PCLK signal is resumed.
FIG. 7 is a timing diagram that illustrates the termination of the PCLK signal according to the prior art. In particular, the CKE signal transitions to a low, and thereby generates a PCKETTL signal in the high state. On the next falling edge of the CLKA signal, the PCKE signal transitions to a low state. Subsequently, the generation of the PCLK signal is terminated. Furthermore, the PCKE signal remains in the low state for subsequent transitions of the CLKA signal. Consequently, the PCLK signal is not generated during those subsequent CLKA cycles.
As described above, the synchronous operation in an integrated circuit memory device may be accomplished using a system clock and a synchronous clock enable provided to the integrated circuit memory device. During testing however, the test system may need to supply the clock signal and the clock enable to the integrated circuit memory device under test. Furthermore, to achieve relative efficiency, numerous integrated circuit memory devices may be tested simultaneously. The tester may therefore be required to supply corresponding clock signals and clock enable signals to each of the integrated circuit memory devices undergoing testing.
The tester may therefore require an output channel for each clock and clock enable signal provided to the integrated circuit memory devices undergoing testing. As the number of integrated circuit memory devices undergoing testing increases, so may the number of channels required to provide corresponding clock signals and clock enable signals to the integrated circuit memory devices. As the number of channels increases, fewer integrated circuit memory devices may be tested simultaneously.
In view of the above discussion, there continues to exist a need to improve the efficiency in testing integrated circuit memory devices.